Conventional electronic data memories, such as DRAM or Flash-RAM, are facing certain limitations as demands to modern data memories are steadily increasing. Above all, modern data memories must meet the requirement to combine a high density of information, fast memory access speed, and non-volatility. The latter non-volatility is increasingly important, since the memory content must be reliably maintained without supplying energy in—for example—mobile applications.
Present electronic data memory concepts, such as the DRAM or the Flash-RAM, store the data in information units based on charged or uncharged capacitors. In the case of a DRAM, these capacitors must be refreshed continuously, as they are kept small in order to achieve a high density of information. Therefore, a separate electronic circuitry for constant reading and rewriting of the information content is necessary.
Increasing the capacitors' size, as in a Flash-RAM, allows for the storage of information for a longer time span. The increased size of the data storage units however, then substantially limits integration and access speed. Additionally, higher operating voltages are required in a Flash-RAM, which further impose restrictions on integration and access speed.
In order to combine non-volatility with fast access and high integration, alternatives to the DRAM and the Flash-RAM are subject to intense scientific and industrial research. Amongst others, the so-called resistive data storage media are most promising candidates for such a replacement and an enhancement of current technologies.
Resistive data memories take advantage of various physical effects to cause a distinguishable and stable change of the electric resistance of special material systems. These systems include, for example, perovskite materials, phase change materials, and the so-called solid electrolytes. Memory cells employing solid electrolytes are also known as programmable metallization cells (PMC) or conductive brigding cells wherein an entire memory is referred to as CB-RAM. In a solid electrolyte a stable conductive bridging is formed by paths of metal ions being mobile in the solid electrolyte. These paths can be generated and decomposed by means of an electric field.
Similar to a classical DRAM device, a memory device employing a resistive memory medium will comprise memory cells, which are arranged in an array of rows and columns. In this way billions of memory cells are integrated on a single chip. Since a large array of memory cells results in thousands of word and bit lines, it is furthermore desirable to pool a set of bit lines in order to simplify the external electronic circuitry. This pooling is usually carried out by means of a multiplexing unit, which connects one bit line out of a set of bit lines to an evaluation unit, while disconnecting the remaining bit lines.
Although the integration of a multiplexing unit greatly simplifies the handling of large numbers of bit lines, only one bit line out of a set of bit lines is connected to an output port at a time. The remaining bit lines are disconnected from all external circuitry and hence may electrically float. This usually results in an undesired charging of the respective bit lines, which is mainly due to capacitive coupling between neighbouring bit lines and leakage currents.
When a floating bit line is to be evaluated it must be first discharged and brought to a respective potential. Since the measured potential of a bit line eventually determines the logical state of the memory cell during a reading operation, compensation for parasitic charging effects of the bit lines must be suppressed. One method for eliminating these undesired charging effects is to connect a bit line to the evaluation unit by a multiplexing unit and to wait until all parasitic charge on the bit line has levelled trough the low impedance of the evaluation unit. This method requires additional time for every reading operation and hence strongly limits access speed and performance of the memory device.